In fabricating semiconductor devices, interconnects that transmit signals from a circuit side of a substrate, which is also conventionally referred to as the “active surface,” to a back side of the substrate are sometimes utilized. Interconnects that extend through the substrate from the circuit side to the back side are sometimes referred to as through interconnects. During fabrication of the semiconductor devices at the wafer level, through interconnects are sometimes referred to as through wafer interconnects (“TWI”) or through silicon interconnects. The through interconnects are typically metal-filled vias formed in the substrate and are configured and positioned to electrically connect integrated circuits on the circuit side to electrical elements on the back side. The back side includes terminal contacts in electrical communication with the through interconnects, sometimes directly and sometimes through redistribution conductors.
As semiconductor devices become smaller and have higher input/output configurations, semiconductor manufacturers must fabricate through interconnects having increasingly smaller sizes and pitches without compromising performance. Through interconnects having a high electrical conductivity and a low parasitic capacitance provide the best performance. In addition to having good performance characteristics, it is advantageous for though interconnects to be capable of fabrication at the wafer level using conventional equipment and conventional processes. It is also advantageous to utilize as few process acts as possible in the fabrication of the semiconductor device to minimize costs and reduce defects. Conventional metal-filled through interconnects utilize multiple photopatterning acts, and may include both front side and back side processing. For example, the terminal contacts and pads for the terminal contacts are made separately utilizing multiple photopatterning acts, which adds considerable cost to the overall fabrication costs.
In order to achieve circuit continuity, a wafer upon which the semiconductor devices are ultimately to be formed is carefully aligned with a reticle or mask before conducting the photopatterning acts. Alignment is conventionally accomplished using a wafer stepper or aligner, which transfers a desired pattern from the reticle or mask onto a material present on the wafer. The wafer stepper uses alignment marks, also characterized as fiducials, on the wafer as a reference point to precisely align the reticle or mask to previously formed materials on the wafer. The alignment marks are typically formed on unused portions of the wafer, such as along a peripheral edge of the wafer or near scribe lines that separate locations of individual semiconductor dice, by etching a pattern of trenches in the underlying layer with a known orientation and spatial relationship. The wafer stepper typically uses light with a fixed wavelength to detect the position of the alignment marks on the wafer.
While conventional alignment processes are efficacious for many applications, these alignment processes are not reliable for back side processing of semiconductor devices having terminal contacts on the back side. Back side processing typically includes patterning and curing of a dielectric material on the back side of the substrate. The dielectric material functions as an etch mask for forming deep vias in the substrate. Openings, other than the vias, that extend through the dielectric material and expose underlying or overlying materials, such as any alignment marks, transfer to the substrate during subsequent processing acts, causing downstream processing issues. In addition, if a metal seed layer is present on the back side, then infrared (“IR”) alignment techniques can not be used to align the front side alignment marks. IR techniques are currently used for back side alignment because the silicon substrate is transparent, which enables back side alignment using the alignment marks on the circuit side of the wafer. However, the metal seed material is not transparent to IR and, therefore, the metal seed material prevents subsequent alignment during the back side processing. To address this problem, unique vias or sets of unique vias can be formed on he back side of the substrate and used as alignment marks. These vias have a unique shape and pattern compared to other vias present on the substrate or on adjacent semiconductor dice. However, forming and detecting the unique vias in a consistent manner has proven to be an unreliable technique, leading to misalignment.